Patents

• Seunghyun Lee “TRANSISTOR STRUCTURE INCLUDING AS-GROWN GRAPHENE AND SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR STRUCTURE” US Patent with Samsung

• Seunghyun Lee, “CONDUCTIVE WIRES AND INTETCONNECT STRUCTURE AND INTEGRATED CIRCUIT DEVICE STRUCTURE” US Patent with Samsung

• Seunghyun Lee, “TERNARY CONTENT ADDRESSABLE MEMORY BASED ON RESISTIVE MEMORIES AND METHOD OF FABRICATING THE SAME”

• Seunghyun Lee, Batyrbek et al “SOLVENT FREE PATTERING METHOD OF QUNATUM DOTS” 10-2022-0180379

• Seunghyun Lee, Batyrbek et al “SEMICONDUCTOR DEVICE BASED ON TERNARY PRECISION XNOR LOGIC AND NEUROMORPHIC COMPUTING SYSTEM INCLUDING THE SAME” 10-2021-0165347

• Seunghyun Lee, Jinho Lim “CONTACT ENGINEERING OF VERTICALLY GROWN DENDRITIC NANOMATERIALS WITH TUNNELING INSULATORS” 10-2021-0074177

• Seunghyun Lee, Z.Zhong et. al “UNIFORM MULTILAYER GRAPHENE BY CHEMICAL VAPOR DEPOSITION” US 10,886,126 B2

• Seunghyun Lee, Dasom Jeon “TRANSISTOR HAVING 2D MATERIALS AS GATE INSULATORS FOR HIGHLY EFFICIENT HEAT TRANSFER” 10-2020-0160087

• Seunghyun Lee, et. al. “DETERMINISTIC VERTICAL RRAM WITH EDGE ELECTRODES” 10-2020-0025110

• Seunghyun Lee, Jinho Lim “METHOD OF MANUFACTURING A RES2 THIN LAYER AND METHOD OF MANUFACTURING A PHOTODETECTOR USING THE SAME” 10-2020-0025103

• Seunghyun Lee, Shem Seo “LOW-POWER SELECTOR WITH GRAPHENE EDGE” 10-2020-0025108

• Seunghyun Lee, Joon Sohn, H.-S. Philip Wong “METAL OXIDE RESISTIVE MEMORY WITH 2-DIMENSIONAL EDGE ELECTRODES” US 10,672,604 B2

• Seunghyun Lee, Chiyui Ahn, Scott Fong, Yongsung Kim, Aditya Sood, Christopher Neumann, Mehdi Asheghi, Kenneth Goodson, Eric Pop, and H. -S. Philip Wong “ ENERGY-EFFICIENT PHASE CHANGE MEMORY WITH GRAPHENE AND 2D MATERIALS AS THERMAL BARRIERS” US 9,583,702 B2

• Seunghyun Lee, Zhaohui Zhong, “FLEXIBLE GRAPHENE BASED MODULATORS” (U.S. Serial No. 61/675,900),

• Seunghyun Lee, Kyunghoon Lee, Zhaohui Zhong, “UNIFORM MULTILAYER GRAPHENE BY CHEMICAL VAPOR DEPOSITION” US 10,886,126 B2

• Seunghyun Lee, et. al. “그래핀 실리콘 접합 트랜지스터” 10-210971